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Microchip Technology /ATSAMV71N21 /SCB /CSSELR

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Interpret as CSSELR

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (DATA)IND 0LEVEL

IND=DATA

Description

Cache Size Selection Register

Fields

IND

selection of instruction or data cache

0 (DATA): Data cache

1 (INSTRUCTION): Instruction cache
LEVEL

cache level selected

Links

()

Register Reference

https://github.com/cmsis-svd/cmsis-svd-data